Presentation
Accelerated ESD Sign-Off Solution: An Efficient and Scalable Approach
DescriptionEarly detection of potential ESD issues is crucial for enhancing overall design robustness and ensuring a high-quality sign-off. Achieving this with full-chip level analysis using native Pathfinder tool is hindered by several factors such as runtime and memory usage demands,complexity of parsing multiple inputs, debuggability through GUI etc..
In an attempt to mitigate these issues, the following approaches were adopted, each with its own caveats:
-Block level ESD closure -> doesn't guarantee ESD protection at full-chip level.
-GDS based simulators for full-chip level sign-off:
1. Requires a clean LVS database, which is available late in the project cycle
2. Flattening design to the transistor level negatively impacts runtime.
This presentation unveils a solution to the challenges of current ESD sign-off processes using Pathfinder-SC technology and helped mitigate ESD problems related to grid robustness,connectivity to bumps and placement coverage early in the project cycle.The resistance computation was also found to be more accurate than traditional extraction tools used. By leveraging this,we were able to extend the resistance checks to encompass not only ESD cells but also macros(Analog IPs, IOs, PLL etc.).This resulted in broader coverage across the full-chip, leading to greater confidence in the sign-off process.
In an attempt to mitigate these issues, the following approaches were adopted, each with its own caveats:
-Block level ESD closure -> doesn't guarantee ESD protection at full-chip level.
-GDS based simulators for full-chip level sign-off:
1. Requires a clean LVS database, which is available late in the project cycle
2. Flattening design to the transistor level negatively impacts runtime.
This presentation unveils a solution to the challenges of current ESD sign-off processes using Pathfinder-SC technology and helped mitigate ESD problems related to grid robustness,connectivity to bumps and placement coverage early in the project cycle.The resistance computation was also found to be more accurate than traditional extraction tools used. By leveraging this,we were able to extend the resistance checks to encompass not only ESD cells but also macros(Analog IPs, IOs, PLL etc.).This resulted in broader coverage across the full-chip, leading to greater confidence in the sign-off process.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall