Presentation
Accurate Memory IR Sign-Off at Lower Tech nodes
DescriptionTechnology advancements in lower tech nodes have increased the complexity of Memory IR closure due to increasing power density, reduced Vmin headroom causing high risk of failure. This presentation explores the challenges and solutions for Memory IR sign-off, focusing on accurate modeling, realistic use-case scenarios, and efficient resource utilization.
The Memory IR sign-off process requires four pillars: IR Modeling, IR Simulation Scenario, IR Reporting, and IR Fixing.
Key aspects of our approach include:
1. Utilizing both abstract and detailed models (based on the memory risk factor) for accurate IR modeling.
2. Selecting realistic test cases for IR simulation by considering memory modes, load capacitance, and the number of toggling bits to ensure realistic IR analysis.
3. Refining default IR drop reported by removing tool pessimism. Introduces a Bbox-based approach to identify the worst-case power and ground drop, considering current charge-discharge locations
4. Implementing effective IR fixing strategies including PG-based fixing methods and timing-based fixes.
By employing detailed models for critical memories, efficiently utilizing PG resources for dual-rail memories, and removing simulation/reporting pessimism, we achieve a seamless Memory IR sign-off process. This approach leads to greater confidence in the sign-off process and ensures robust chip performance at lower technology nodes.
The Memory IR sign-off process requires four pillars: IR Modeling, IR Simulation Scenario, IR Reporting, and IR Fixing.
Key aspects of our approach include:
1. Utilizing both abstract and detailed models (based on the memory risk factor) for accurate IR modeling.
2. Selecting realistic test cases for IR simulation by considering memory modes, load capacitance, and the number of toggling bits to ensure realistic IR analysis.
3. Refining default IR drop reported by removing tool pessimism. Introduces a Bbox-based approach to identify the worst-case power and ground drop, considering current charge-discharge locations
4. Implementing effective IR fixing strategies including PG-based fixing methods and timing-based fixes.
By employing detailed models for critical memories, efficiently utilizing PG resources for dual-rail memories, and removing simulation/reporting pessimism, we achieve a seamless Memory IR sign-off process. This approach leads to greater confidence in the sign-off process and ensures robust chip performance at lower technology nodes.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall