Presentation
Effective Ways of Analyzing and Optimizing Voltage Variation Challenges for 3DIC Chips
DescriptionIn consumer products, there is a pursuit of low power consumption and small size. In the case of this article, to enhance the computing power per unit area of the chip, multiple Storage dies and a Logic die are stacked vertically. Each Die contains tens of thousands of high-precision array units, storage array units, and digital units. The requirements for voltage variation on the power supply and VSS are extremely strict.
Due to the limitation of bump resources, the VSS of the Storage and Logic Dies are combined on the Logic Die and then fan out to the VSS Bumps. It is necessary to simultaneously simulate the voltage variation of the VSS TSV(Through Silicon Via) at each grounding point location on the Storage Dies and the Logic DIE and then analyze and find an optimization scheme for the voltage variation.
In this presentation, we provides an effective analysis method for the Full Chip Voltage Variation of complex analog-digital hybrid Storage 3DIC, which can accurately analyze the voltage variation of VSS TSV at the grounding point locations.
Then, two optimization methods are presented.
The first one is we optimizes the voltage variation of the power ground of the storage array by means of the controlled delayed startup of array units. Using the method provided in this paper, the effectiveness of the scheme is demonstrated through the comparison of simulation data.
The second one is through comparative analysis of simulation data, we demonstrate that the mutual inductance between TSV Cells cannot be ignored in multi-die stacking. Meanwhile, an arrangement scheme was provided that can reduces the mutual inductance between TSV cells effectively.
Due to the limitation of bump resources, the VSS of the Storage and Logic Dies are combined on the Logic Die and then fan out to the VSS Bumps. It is necessary to simultaneously simulate the voltage variation of the VSS TSV(Through Silicon Via) at each grounding point location on the Storage Dies and the Logic DIE and then analyze and find an optimization scheme for the voltage variation.
In this presentation, we provides an effective analysis method for the Full Chip Voltage Variation of complex analog-digital hybrid Storage 3DIC, which can accurately analyze the voltage variation of VSS TSV at the grounding point locations.
Then, two optimization methods are presented.
The first one is we optimizes the voltage variation of the power ground of the storage array by means of the controlled delayed startup of array units. Using the method provided in this paper, the effectiveness of the scheme is demonstrated through the comparison of simulation data.
The second one is through comparative analysis of simulation data, we demonstrate that the mutual inductance between TSV Cells cannot be ignored in multi-die stacking. Meanwhile, an arrangement scheme was provided that can reduces the mutual inductance between TSV cells effectively.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall