Presentation
Automated Topology based Pin Access Checker for Correct by Construction Standard Cells Design
DescriptionPin accessibility is crucial in semiconductor layout development. As process nodes shrink, achieving a compact layout with high yield is essential, involving tightly packed routing and device placement within the standard cell. Ensuring pins have adequate clearance for connections becomes challenging, especially with fewer metal layers. Issues with pin accessibility during placement and routing can significantly prolong the development cycle.
This paper introduces a novel technique to validate standard cells by placing them in topologies that mimic the SoC congestion environment, using the same router engine and rules as during actual Placement and Routing. The simple, repetitive topologies result in comparable and probabilistic routing results, indicating the quality of standard cells in various placement scenarios. These topologies could involve the same cell repeating in different orientations or a central DuT with varying surrounding cells. The flow sweeps across selected cells to generate all such topologies using fillers for uniform placement of DuT. DRC and the number of vias used are reported for comprehensive analysis. This method safeguards the detection of pin accessibility issues during the standard cell layout development cycle, ensuring standard cells are free from pin accessibility problems upon construction.
This paper introduces a novel technique to validate standard cells by placing them in topologies that mimic the SoC congestion environment, using the same router engine and rules as during actual Placement and Routing. The simple, repetitive topologies result in comparable and probabilistic routing results, indicating the quality of standard cells in various placement scenarios. These topologies could involve the same cell repeating in different orientations or a central DuT with varying surrounding cells. The flow sweeps across selected cells to generate all such topologies using fillers for uniform placement of DuT. DRC and the number of vias used are reported for comprehensive analysis. This method safeguards the detection of pin accessibility issues during the standard cell layout development cycle, ensuring standard cells are free from pin accessibility problems upon construction.
Authors
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall