Presentation
Boosting Low Power Verification Methodology: Introducing Power-Aware Formal Property Verification into the Flow
DescriptionThe increasing complexity of System on Chip (SoC) designs over the years has necessitated advanced verification techniques to detect hidden functional failures. This challenge becomes even tougher when low power elements such as isolation cells, level shifters are present in the design.
The low-power integrated circuit market is experiencing significant growth, driven by the portable and battery-powered chip demand. In such applications, the low-power aspect is an essential component of the design cycle. Consequently, a great care must be paid during the verification phase to guarantee the correct functionality of the low-power architecture. For example, a bug in the isolation protocol could potentially cause a complete system failure.
This paper proposes a methodology employing formal approach for verifying potential criticalities such as supply network issues, isolation and retention in low-power chips. The proposed strategy was applied to an ultra low-power SoC (250k equivalent gates) based on ARM Cortex M0+ and featuring a compound power structure with five switchable domains, designed by ST. The verification time is dramatically reduced (~50%) compared to dynamic approach, also improving verification quality. During this work, a risky bug that was extremely difficult to reproduce in a simulative environment was identified early in the flow.
The low-power integrated circuit market is experiencing significant growth, driven by the portable and battery-powered chip demand. In such applications, the low-power aspect is an essential component of the design cycle. Consequently, a great care must be paid during the verification phase to guarantee the correct functionality of the low-power architecture. For example, a bug in the isolation protocol could potentially cause a complete system failure.
This paper proposes a methodology employing formal approach for verifying potential criticalities such as supply network issues, isolation and retention in low-power chips. The proposed strategy was applied to an ultra low-power SoC (250k equivalent gates) based on ARM Cortex M0+ and featuring a compound power structure with five switchable domains, designed by ST. The verification time is dramatically reduced (~50%) compared to dynamic approach, also improving verification quality. During this work, a risky bug that was extremely difficult to reproduce in a simulative environment was identified early in the flow.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall