Presentation
Novel Shift-Left Methodology for System Power Integrity Analysis with Early Chip Power Model
DescriptionIn complex systems such as Multi-Chip Modules where high speed digital and analog ICs are interconnected, the Power Integrity (PI) analysis is a key step for design sign-off. Chip, package and board back annotation optimization may have dramatic impact on the project schedule and cost if the power integrity constraints are not anticipated.
The Chip Power Model (CPM) is one of the key contributors along with the package and board models that enable the system PI analysis. It is generally generated when the design is almost frozen, and any modifications would result in significant impact on the product design. Thus, anticipation is key for the design success.
This paper highlights an approach to enable PI analysis at very early design stage allowing to anticipate the design feedback. It is based on the generation of a CPM from an array of blocks which have a representative behavior for the device. The block activity is tuned with respect to the expected power profile and the number of blocks instances is sized according to the design area. Simulation results show the need to create the complete CPM at top level instead of combining the standalone block CPMs.
The Chip Power Model (CPM) is one of the key contributors along with the package and board models that enable the system PI analysis. It is generally generated when the design is almost frozen, and any modifications would result in significant impact on the product design. Thus, anticipation is key for the design success.
This paper highlights an approach to enable PI analysis at very early design stage allowing to anticipate the design feedback. It is based on the generation of a CPM from an array of blocks which have a representative behavior for the device. The block activity is tuned with respect to the expected power profile and the number of blocks instances is sized according to the design area. Simulation results show the need to create the complete CPM at top level instead of combining the standalone block CPMs.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall