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Chip reliability with antenna discharge path consideration
DescriptionIt is widely understood in the semiconductor design and manufacturing industry that antenna-related failure results from negatively charged particles occurring during metal interconnect etching discharging through the point of least resistance on the path. When the antenna discharge issue was discovered, the solution to avoid such failures was editing the layout so that the ratio of metal area to combined gates and diodes area was greater than the acceptable antenna ratio value determined by the foundry.
In deep sub-micron manufacturing, antenna analysis has become much more complicated. As such, a computation-based method to estimate the potential damages is used. Accurate antenna analysis on a very large design requires computing resources. The antenna model is often simplified using some design assumptions, compromising accuracy for engineering time and cost of computing resources. To be fair, the foundry that creates the antenna models and rule checks can not anticipate all possible design structures that cause antenna failures. However, the designers may be able to improve the reliability of their chip by adding the proposed concept of customized antenna checking.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall