Presentation
Pattern-based Abstraction for Mixed Transistor-Level Static Timing Analysis
DescriptionTransistor-level static timing analysis plays a vital role in IBM high-performance processors' design, allowing custom circuits to meet aggressive frequency and power goals. It enables designers to robustly determine timing critical paths based on simulation of transistor-level netlist incorporating logic and layout parasitic effects in advanced process nodes.
Previously, due to analog nature or capacity concerns combined with extractor limitations, designers had to abstract large portions of designs. "Grey boxing" could easily miss real layout problems or mis-estimate effects inside abstracts.
This talk will present a pattern-based abstraction timing methodology for mixed transistor-level and abstract-based static timing analysis, which has been successfully leveraged by IBM in multiple microprocessor generations. This novel approach ensures truly layout-based timing analysis and rule generation by providing flexibility to precisely control timing abstraction on subsets of a netlist while modelling parasitic effects at transistor level, achieving higher accuracy than prior methods. This methodology has enhanced both design and EDA productivity with early enablement of circuits and easier support of complicated subcircuits; and it has reduced analysis runtime by 3.7X to 9.6X, leading to faster timing signoff and earlier delivery of rules to integrators.
Previously, due to analog nature or capacity concerns combined with extractor limitations, designers had to abstract large portions of designs. "Grey boxing" could easily miss real layout problems or mis-estimate effects inside abstracts.
This talk will present a pattern-based abstraction timing methodology for mixed transistor-level and abstract-based static timing analysis, which has been successfully leveraged by IBM in multiple microprocessor generations. This novel approach ensures truly layout-based timing analysis and rule generation by providing flexibility to precisely control timing abstraction on subsets of a netlist while modelling parasitic effects at transistor level, achieving higher accuracy than prior methods. This methodology has enhanced both design and EDA productivity with early enablement of circuits and easier support of complicated subcircuits; and it has reduced analysis runtime by 3.7X to 9.6X, leading to faster timing signoff and earlier delivery of rules to integrators.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall