Presentation
Contemporary PPAS Optimization Strategies in Physical Implementation of Digital SoCs – A Case Study
DescriptionToday, System on Chip (SoC) devices have stringent Power, Performance, Area and Schedule (PPAS) requirements. With the increase in design size and complexity, standard techniques and flow-options provided by state-of-the-art Placement and Routing (PnR) tools often prove to be ineffective. It is really important to have better design approach and optimization techniques while considering signoff constraint on timing closure and physical verification.
With each design revision there is a push to improve on the PPAS met by the previous generation. Although design related changes are the most effective for this, beyond a point to get the maximum out of a technology, we need to look at novel and automated strategies that can be used in physical design implementation.
In this paper, we are exploiting various methodologies and optimization techniques which can be used across different implementation stages of physical design cycle. We demonstrate end-to-end implementation of various optimization techniques for Turn-Around-Time (TAT) improvement, without any impact to Quality-of-Results (QOR). We also present a deep dive analysis of a novel solution to the primitive problem of multiple iterations required to close timing for Source Synchronous IO Interfaces.
In this paper, we will discuss about the correlation issues which are prevalent among implementation and sign-off techniques and the various methodologies that can help in reducing this miscorrelation which in turn can lead to PPAS improvements.
With each design revision there is a push to improve on the PPAS met by the previous generation. Although design related changes are the most effective for this, beyond a point to get the maximum out of a technology, we need to look at novel and automated strategies that can be used in physical design implementation.
In this paper, we are exploiting various methodologies and optimization techniques which can be used across different implementation stages of physical design cycle. We demonstrate end-to-end implementation of various optimization techniques for Turn-Around-Time (TAT) improvement, without any impact to Quality-of-Results (QOR). We also present a deep dive analysis of a novel solution to the primitive problem of multiple iterations required to close timing for Source Synchronous IO Interfaces.
In this paper, we will discuss about the correlation issues which are prevalent among implementation and sign-off techniques and the various methodologies that can help in reducing this miscorrelation which in turn can lead to PPAS improvements.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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