Presentation
Improving Digital Design performance and area using DSO.ai
DescriptionWith the increase in the performance of devices like smartphones and wearables, the need to reduce their size also grows. A crucial aspect of developing the digital portion of these chips is physical synthesis. The integration of artificial intelligence into the back-end flow has been considered, aiming to achieve improvements in performance, power, and area.
The Design Space Optimization (DSO.ai) tool by Synopsys is a machine-learning application that explores the design search space and evaluates outcomes based on user-defined metrics. This AI application increases designer productivity while reducing the need for human and computational resources.
The tool has been embedded in a back-end flow to explore different design solutions for the STPMIC25 device by STMicroelectronics. Due to the limited routing resources, the critical point of the design is congestion. This results in a relatively low utilization ratio with a large amount of empty area in the floorplan. The tool finalizes the design without DRC violations, with congestion values that allow for possible future metal fixes and a potential area reduction of 7%.
The proposed flow may be adopted in the development of a device to explore new design solutions achieving improvements in the metrics of interest.
The Design Space Optimization (DSO.ai) tool by Synopsys is a machine-learning application that explores the design search space and evaluates outcomes based on user-defined metrics. This AI application increases designer productivity while reducing the need for human and computational resources.
The tool has been embedded in a back-end flow to explore different design solutions for the STPMIC25 device by STMicroelectronics. Due to the limited routing resources, the critical point of the design is congestion. This results in a relatively low utilization ratio with a large amount of empty area in the floorplan. The tool finalizes the design without DRC violations, with congestion values that allow for possible future metal fixes and a potential area reduction of 7%.
The proposed flow may be adopted in the development of a device to explore new design solutions achieving improvements in the metrics of interest.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall