Presentation
Enhancing Design Quality through a High-Level Synthesis Flow in Neural Network-Based Keyword Spotting Systems
DescriptionHigh-Level Synthesis (HLS) offers significant advantages over traditional design methodologies in implementing complex digital systems. This work, conducted jointly with Politecnico di Milano, demonstrates these benefits through the design of a Keyword Spotting System (KWS) that recognizes eight short vocal commands using SystemC modeling along with the Cadence Stratus HLS tool.
The basic structure of this KWS design includes a Mel-Frequency Cepstral Coefficients (MFCC) module for feature extraction and a Deep Neural Network (DNN) module for command recognition.
Once the baseline design is ready, this flow allows to easily implement different optimized versions of the design. This is done by adding Stratus HLS tool directives at key points inside the SystemC code and/or activating specific tool options (e.g., for low power optimizations). Several versions of the KWS design were analyzed by selectively enabling power, area, and performance optimizations. Every optimized version of the design was successfully synthesized considering a clock frequency between 100 and 400 MHz.
The proposed HLS flow not only accelerates the design cycle, but also permits to optimize the design even in advanced stages with minimal impact on the time schedule. Specifically, it enables the exploration of multiple architectural solutions, optimizing latency, throughput, area, and power consumption.
The basic structure of this KWS design includes a Mel-Frequency Cepstral Coefficients (MFCC) module for feature extraction and a Deep Neural Network (DNN) module for command recognition.
Once the baseline design is ready, this flow allows to easily implement different optimized versions of the design. This is done by adding Stratus HLS tool directives at key points inside the SystemC code and/or activating specific tool options (e.g., for low power optimizations). Several versions of the KWS design were analyzed by selectively enabling power, area, and performance optimizations. Every optimized version of the design was successfully synthesized considering a clock frequency between 100 and 400 MHz.
The proposed HLS flow not only accelerates the design cycle, but also permits to optimize the design even in advanced stages with minimal impact on the time schedule. Specifically, it enables the exploration of multiple architectural solutions, optimizing latency, throughput, area, and power consumption.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall