Presentation
Hierarchical Early Latchup Checking Flow
DescriptionWhen integrating high voltage IOs into designs, areas around the IO driver have an increased exposure to latchup effects, due to higher concentrations of charge carriers injected into the chip by the IO. These exposed areas have requirements for denser welltap cell coverage to sink the additional carriers, and other macros that are victims to these latchup aggressors must be kept away. As chip content continues to grow, physical integration requires additional levels of hierarchy and these rules become more complicated, as they must be tracked across hierarchical boundaries. Latchup rules are checked as part of signoff DRC, but due to the need to cleanly assemble the full chip, it is often not possible to perform these checks until late in design phases. This presentation details an automated flow for pushing latchup shapes in a parent context down into child block context, considering multiple levels of hierarchy, re-use, orientations, as well as enhanced welltap insertion, LEF generation with latchup victim shapes, and hierarchical checking of latchup aggressor to victim interactions. This process is integrated into the PnR tool flow so that it can be seamlessly run directly as part of floorplanning to catch latchup related placement issues much earlier.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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