Presentation
HeatSync: Machine Learning-Driven Floorplanning for Optimized Power Integrity and Thermal Integrity in Advanced Packages
DescriptionThe increasing demand for high-performance and power-efficient systems presents critical challenges in optimizing power integrity (PI) and thermal integrity (TI) within advanced packages. The trade-off between PI and TI is exacerbated in multi-core xPU architectures, where thermal coupling and power domain constraints limit traditional engineer-driven methods. To address these issues, we propose HeatSync, a reinforcement learning (RL)-based framework for simultaneous optimization of PI and TI.
HeatSync employs an efficient thermal resistance matrix-based evaluator to replace traditional computational fluid dynamics tools, achieving over 500× faster computation with less than 2% error. The RL framework can optimize floorplan configurations and types of decoupling capacitors and their placement, balancing PI and TI objectives through user-defined weighting factors. In a simulation environment with 5536 floorplans and four decoupling capacitor configurations, the proposed method demonstrated up to 8.3% improvement in overall performance figure of merit. By minimizing maximum temperature, hot spot areas, and impedance, HeatSync alleviates the trade-offs between PI and TI, providing scalable and time-efficient optimization.
This work provides a foundation for PI and TI optimization in next-generation semiconductor designs. Future work will focus on a two-way coupled RL framework for detailed PI-TI analysis and extending to 3D packages to address nonlinear thermal behaviors.
HeatSync employs an efficient thermal resistance matrix-based evaluator to replace traditional computational fluid dynamics tools, achieving over 500× faster computation with less than 2% error. The RL framework can optimize floorplan configurations and types of decoupling capacitors and their placement, balancing PI and TI objectives through user-defined weighting factors. In a simulation environment with 5536 floorplans and four decoupling capacitor configurations, the proposed method demonstrated up to 8.3% improvement in overall performance figure of merit. By minimizing maximum temperature, hot spot areas, and impedance, HeatSync alleviates the trade-offs between PI and TI, providing scalable and time-efficient optimization.
This work provides a foundation for PI and TI optimization in next-generation semiconductor designs. Future work will focus on a two-way coupled RL framework for detailed PI-TI analysis and extending to 3D packages to address nonlinear thermal behaviors.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall