Presentation
Autonomous Physical Design: Accelerating ASIC Design using Machine Learning
DescriptionAs the complexity of Application-Specific Integrated Circuit (ASIC) design continues to increase, traditional Electronic Design Automation (EDA) tools face significant challenges in efficiently managing the physical design process. Our work introduces a machine learning-driven framework aimed at accelerating the Placement and Routing (PnR) stages of the RTL-to-GDSII flow. By incorporating reinforcement learning and predictive models, the framework automates input recommendations, QoR predictions, and resource allocation, providing a more efficient and scalable approach to ASIC design. The use of machine learning enables the framework to optimize design parameters, reduce design time, and improve overall design quality. This research demonstrates the potential of machine learning to enhance the design process, addressing the growing demands of modern semiconductor development and enabling the creation of complex, high-performance ASICs.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall