Presentation
Novel Methodology to Address ESD Verification Complexity of 2.5D/3D-IC Designs
DescriptionAs the adoption of 2.5D/3D-ICs increases, it is essential to address new challenges that differ from those in conventional 2D-ICs.
There are two primary issues in 2.5D/3D-IC ESD verification: increased verification complexity and cost. It is necessary to check paths not only within a single die but also between dies, considering the integration of dies with different specifications, such as technology nodes and ESD immunity levels (HBM/CDM).
The number of bumps is increasing and is expected to reach millions with hybrid bond technology, leading to a dramatic increase in check paths, verification time, and debugging/feedback costs.
To address these challenges, we developed an ESD verificationenvironment that reduces verification complexity in large-scale 2.5D-ICs and improves cost efficiency through two key processes.
For a large number of resistance checks between micro bumps, we programmatically reduced verification time by extracting optimal check regions based on cell placements and bump positions. Additionally, by mapping and visualizing the resistance check results between micro bumps, we clarified layout weaknesses and facilitated easier layout fixes.
There are two primary issues in 2.5D/3D-IC ESD verification: increased verification complexity and cost. It is necessary to check paths not only within a single die but also between dies, considering the integration of dies with different specifications, such as technology nodes and ESD immunity levels (HBM/CDM).
The number of bumps is increasing and is expected to reach millions with hybrid bond technology, leading to a dramatic increase in check paths, verification time, and debugging/feedback costs.
To address these challenges, we developed an ESD verificationenvironment that reduces verification complexity in large-scale 2.5D-ICs and improves cost efficiency through two key processes.
For a large number of resistance checks between micro bumps, we programmatically reduced verification time by extracting optimal check regions based on cell placements and bump positions. Additionally, by mapping and visualizing the resistance check results between micro bumps, we clarified layout weaknesses and facilitated easier layout fixes.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall