Presentation
On-Die Power Noise impact on High-Speed Signal Integrity (SI) of Photonics computing chip base on 3D Heterogeneous Integration
DescriptionWith the development of new high-speed interconnect technologies and applications, along with the introduction of 3D packaging, chip design and simulation have become increasingly complex. In high performance optoelectronic chips, the quality of electrical signals directly determines the modulation performance of optical signals, the impact of power noise from Chiplets, packaging, and PCBs on signal integrity has become increasingly significant.
Traditional IBIS workflows have limitations in addressing complex issues such as on-chip power decoupling. To address this, we propose a new simulation workflow based on IBIS Model and Chip Power Model (CPM) to analyze the coupled effects of signals and power. By integrating TSV Spice Model, Chip Macro Model (CMM) for analog circuits, we construct a comprehensive CPM. Then combined with the extracted S-parameters of packaging and PCB, enables system-level simulations that holistically consider the sign-off factors affecting signal integrity.
This workflow is faster and more practical. Experimental results demonstrate that when CPM-based power noise simulation is kept within a certain range, the eye diagram of signal integrity shows significant improvement and exhibits stronger correlation with the actual chip performance. This underscores the effectiveness and importance of this method in identifying and resolving signal integrity issues.
Traditional IBIS workflows have limitations in addressing complex issues such as on-chip power decoupling. To address this, we propose a new simulation workflow based on IBIS Model and Chip Power Model (CPM) to analyze the coupled effects of signals and power. By integrating TSV Spice Model, Chip Macro Model (CMM) for analog circuits, we construct a comprehensive CPM. Then combined with the extracted S-parameters of packaging and PCB, enables system-level simulations that holistically consider the sign-off factors affecting signal integrity.
This workflow is faster and more practical. Experimental results demonstrate that when CPM-based power noise simulation is kept within a certain range, the eye diagram of signal integrity shows significant improvement and exhibits stronger correlation with the actual chip performance. This underscores the effectiveness and importance of this method in identifying and resolving signal integrity issues.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall