Presentation
Sign-off Challenges and Solutions in Power Integrity and Reliability Analysis of 2.5DIC Silicon Interposer
DescriptionIn the realm of semiconductor design, ensuring power integrity and reliability analysis in interposer design presents a unique set of challenges. The passive nature of interposers, devoid of SOC data at early and design stage, complicates the analysis of power integrity and reliability. Under the premise of lacking SOC data, performing independent simulations for the interposer becomes crucial. Ensure the sign-off safety of the interposer-only design and improve the sign-off efficiency through the robustness check of the power grid, layer drop analysis, electromigration (EM) assessment, and checks for ESD resistance and current density based on the absence of SOC data.
If the interposer design is led by the packaging team, the delay in SOC data from the digital backend team significantly reduces the optimization efficiency of the interposer design. To address this, we propose a new simulation workflow based on creating probes using micro bumps and providing constant/PWL currents for static/dynamic simulation to check layer drop, PG grid robustness, and power EM. The foundry has ESD rules for the interposer and can separately conduct verification on the resistance and current density between bumps in an "interposer only" manner.
If the interposer design is led by the packaging team, the delay in SOC data from the digital backend team significantly reduces the optimization efficiency of the interposer design. To address this, we propose a new simulation workflow based on creating probes using micro bumps and providing constant/PWL currents for static/dynamic simulation to check layer drop, PG grid robustness, and power EM. The foundry has ESD rules for the interposer and can separately conduct verification on the resistance and current density between bumps in an "interposer only" manner.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall