Presentation
Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
DescriptionAs technology advances to deep sub-micron nodes, the complexity of chip design increases, particularly for high-sigma verification of bandgap references and RC oscillators. Traditional verification workflows are time-consuming and require multiple iterations, significantly delaying project timelines. This paper presents an AI-powered Additive Learning methodology that accelerates verification by retaining and reusing AI models from previous simulation jobs. The proposed methodology, applied to Microchip's iterative workflows, demonstrates up to 20x simulation speedup and 22x wall-clock time reduction without compromising accuracy. By automating the iterative process, this approach enhances both efficiency and accuracy, providing a fast, reliable, and scalable solution for verification in advanced technology nodes.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall