Presentation
Design-for-Verification architecture to shift-left TTM and align test codebase in multi-chiplet SoCs
DescriptionThe rising complexity of chiplet-based SoCs has resulted in significant challenges in the areas of post-silicon test, SLT, bring-up, debug diagnostics, as well as pre-silicon verification. In this presentation, we describe a novel approach, applied to a series of AMD multi-chiplet SoCs, of introducing HW structures in several key areas of SoC design, to align Test, SLT, Debug and Verification in chiplet-based SoCs.
HW-based Design-for-Verification and Validation (DFV) is a novel SoC methodology, reducing silicon test and bring-up efforts by implementing minimal low-footprint architectural changes.
One of the most important outcomes of introducing DfV into multi-chiplet SoCs is the ability to finally leverage the code base from pre-silicon verification testcases with the code used for SoC bring-up, debug and diagnostics.
The presentation details the implementation of a number of DFV techniques that introduce HW-based architectural changes into the design. DFV involves selectively augmenting logic at strategic locations and interfaces of design. Such logic may induce and observe various hard-to-hit scenarios and events to allow isolation of specific sections of multi-chiplet SoCs. System-level test time is thus significantly reduced due to elimination of significant parts of the overall scenario to the system-level event of interest. This process does not alter the original design intent and adds minimal overhead to SoC area footprint.
HW-based Design-for-Verification and Validation (DFV) is a novel SoC methodology, reducing silicon test and bring-up efforts by implementing minimal low-footprint architectural changes.
One of the most important outcomes of introducing DfV into multi-chiplet SoCs is the ability to finally leverage the code base from pre-silicon verification testcases with the code used for SoC bring-up, debug and diagnostics.
The presentation details the implementation of a number of DFV techniques that introduce HW-based architectural changes into the design. DFV involves selectively augmenting logic at strategic locations and interfaces of design. Such logic may induce and observe various hard-to-hit scenarios and events to allow isolation of specific sections of multi-chiplet SoCs. System-level test time is thus significantly reduced due to elimination of significant parts of the overall scenario to the system-level event of interest. This process does not alter the original design intent and adds minimal overhead to SoC area footprint.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall