Presentation
Thermal Aware Design Optimizations and Signoff Using RHSC-Electrothermal
DescriptionEmerging technologies like AI/ML demands for high compute power, increasing the temperature in high activity regions of the chip. It is even more significant in multichip type of system architectures as heat gets trapped between chip interfaces. High temperature will impact performance and reliability of the product and cause possible thermal runaway if thermal cooling solutions cannot bring overall system temperature down. Methodology and flow proposed in this work will accurately model and analyze multiple chip-package thermal scenarios and capture tile based thermal profiles for each die in reasonable runtime. It allows different design metrics to do thermal aware optimizations and signoff product with high confidence.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall