Presentation
Clock H-tree exploration in BSPDN
DescriptionAs node technology has been evolved, routing congestion and net delay issues are becoming more severe.
BSPDN and BS clock routing solution can resolve these challenging by segregating routing area with very low resistance metal.
We propose BS H-tree CTS, which is showing robust timing characteristics by fully enabling back-side metal resources.
The low-resistance of BS metal in BS CTS reduced the clock latency and net delay, and the symmetric structure of H-tree improved the clock skew.
Based on our methodology, the CPU design achieved 5.3% improvement in cell area and 9.7% in performance, and for the GPU design, a 9.6% in cell area and 10.7% in performance.
BSPDN and BS clock routing solution can resolve these challenging by segregating routing area with very low resistance metal.
We propose BS H-tree CTS, which is showing robust timing characteristics by fully enabling back-side metal resources.
The low-resistance of BS metal in BS CTS reduced the clock latency and net delay, and the symmetric structure of H-tree improved the clock skew.
Based on our methodology, the CPU design achieved 5.3% improvement in cell area and 9.7% in performance, and for the GPU design, a 9.6% in cell area and 10.7% in performance.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall