Presentation
Early Clock Network Jitter Estimation
Descriptionclock network jitter signoff simulation takes place at very late phase of the design because of unavailability of simulation vectors, package model, post route, filled design data at early design phases. So, estimated clock network jitter values assumed at initial design phases. Using approximate modelling of power noise waveforms in clock network circuit SPICE simulations, we can predict clock network jitter at early phase of the design (clock routed database). Once accurate clock network device power waveforms (piece wise linear) are available from IR analysis, actual waveforms can be used in clock network circuit SPICE simulation to derive more accurate clock network jitter value. These methods for clock network jitter calculation are scalable and carry minimum dependency on design size
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall