Presentation
A Solution for intermittently and Fastly Power On Repair
DescriptionWith the continuous expansion of the chip scale and the pursuit of enhanced performance, augmenting the memory repair time during the power-up process has become increasingly arduous. This paper presents a novel structure that is designed to curtail the runtime of the memory hard repair process and bolster the efficiency of the full-chip repair dispatcher, thereby facilitating high-speed full-chip repair.
This structure encompasses two principal components: the request scheduler and the Index repair mechanism of the STAR memory system provided by Synopsys. In the case jointly developed by Sanechips and Synopsys, within a repair clock frequency of 100 MHz, the largest subsystem can repair any of three memories within a mere 2.5 microseconds. Moreover, the full-chip repair, with out-of-order decoupling requests, can be accomplished within 5 microseconds.
This structure encompasses two principal components: the request scheduler and the Index repair mechanism of the STAR memory system provided by Synopsys. In the case jointly developed by Sanechips and Synopsys, within a repair clock frequency of 100 MHz, the largest subsystem can repair any of three memories within a mere 2.5 microseconds. Moreover, the full-chip repair, with out-of-order decoupling requests, can be accomplished within 5 microseconds.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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