Presentation
From Block, Chip to System - A Comprehensive flow for large FPGA Dynamic Power Integrity Sign-off
DescriptionField Programmable Gate Array (FPGA) chips have the characteristics of high flexibility and strong parallel processing capabilities. With the FPGA chip scale increasing, more and more configurable logic blocks (CLBs) are designed in it. . Each CLB is composed of multiple look-up tables (LUTs), flip-flops, carry logic, and so on. These logic units can implement various combinational logic and sequential logic functions through programming. These analog modules are instantiated thousands of times within the chip, which also brings great challenges to the dynamic power simulation of such chips. How to get so many analog units to flip and generate accurate currents in the way they actually work without vectors is a big challenge.
This article provides a dynamic simulation idea, which is to make a model for each simulated module, including its physical information and current information in multiple states, and then bring it into the digital circuit simulation environment. By setting the toggle time and state, just like a conductor directing an orchestra, these modules can be directed to toggle in the way they actually work, so as to check the weak points of the chip under working conditions. Meanwhile, a chip power model can be generated for the system to conduct system-level power integrity analysis.
This article provides a dynamic simulation idea, which is to make a model for each simulated module, including its physical information and current information in multiple states, and then bring it into the digital circuit simulation environment. By setting the toggle time and state, just like a conductor directing an orchestra, these modules can be directed to toggle in the way they actually work, so as to check the weak points of the chip under working conditions. Meanwhile, a chip power model can be generated for the system to conduct system-level power integrity analysis.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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