Presentation
An advanced multi-vector optimization methodology to enhance power performance in scaled-down technology nodes.
DescriptionAs technology nodes shrink, the demand for energy-efficient designs increases. Improved power gain ensures that SoCs consume less energy, extending battery life in portable devices and reducing operational costs in high-performance systems. This is essential for applications like AI, IoT, and edge computing. The existing method of defining switching activity often use worst-case or average-case scenarios, which can lead to overestimating or underestimating of power.
Vector based power analysis captures switching activity accurately at granular level, leading to more precise dynamic and leakage power calculations compared to static, generalized assumptions in traditional power analysis. Multiple vectors are generated by simulating RTL, these are properly analyzed based on their active and idle timeframes and merged, to predict accurate activity; to achieve more power compared to using single vector approach. In addition to this, the superset of vectors is replayed and analyzed with a simulator to identifies the areas without accurate activity and generate the fully annotated design for accurate gate-level power. This paper presents a methodology that utilizes switching activity information from multiple vectors, merging power patterns and re-simulating the vectors to accurately annotate the power patter during synthesis and Place & Route to optimize power performance in CPU designs.
Vector based power analysis captures switching activity accurately at granular level, leading to more precise dynamic and leakage power calculations compared to static, generalized assumptions in traditional power analysis. Multiple vectors are generated by simulating RTL, these are properly analyzed based on their active and idle timeframes and merged, to predict accurate activity; to achieve more power compared to using single vector approach. In addition to this, the superset of vectors is replayed and analyzed with a simulator to identifies the areas without accurate activity and generate the fully annotated design for accurate gate-level power. This paper presents a methodology that utilizes switching activity information from multiple vectors, merging power patterns and re-simulating the vectors to accurately annotate the power patter during synthesis and Place & Route to optimize power performance in CPU designs.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall