Presentation
A X-mask Chip Fast Binning Technology
DescriptionTraditional binning methods, especially the observation of test results, make binning have to face the difficulties of analysis. Many existing test solutions, such as Streaming Scan Network, use the shared bus technology. These solutions cannot quickly judge the Pass or Fail of any target circuit from the test result only. Therefore, marking a large number of labels or constructing special patterns become some methods of tracing the detailed test results. However, this is still complicated and not intuitive.
This work proposes a chip fast binning technology. A test solution including MISR, XORs and dr_config is designed to easily obtain the signatures of test results in all target circuits. These signatures can represent the test results. Therefore, the difficulty in obtaining the results of any target circuit can be reduced.
Because of the X-clean requirement of MISR, a X-mask test solution is designed to prevent any X from entering the misr and avoid the additional design load caused by the circuit requirements for the X-tolerant. The X-mask test solution can ensure that the MISR can calculate more reliable test results, reduce the design requirements for the circuits and finally apply to more circuits.
This work proposes a chip fast binning technology. A test solution including MISR, XORs and dr_config is designed to easily obtain the signatures of test results in all target circuits. These signatures can represent the test results. Therefore, the difficulty in obtaining the results of any target circuit can be reduced.
Because of the X-clean requirement of MISR, a X-mask test solution is designed to prevent any X from entering the misr and avoid the additional design load caused by the circuit requirements for the X-tolerant. The X-mask test solution can ensure that the MISR can calculate more reliable test results, reduce the design requirements for the circuits and finally apply to more circuits.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall