Presentation
Mitigating Routing Congestion in Automotive SoCs with ML based Power Grid Optimization
DescriptionWith the increasing design complexity at lower FinFET technology nodes and decreasing noise margins, optimizing the power grid (PG) is crucial for power integrity (PI) signoff in System-on-Chip (SoC) designs. Traditionally, designers rely on Power & Routing (P&R) tools and perform power integrity analysis with PG grid adjustments. However, challenges such as limited parameter selection for Electromigration and Voltage drop (EMIR) sensitivity analysis, long iteration cycles, and insufficient data statistics hinder effective PG grid optimization. This paper proposes a machine learning (ML)-based approach for exhaustive PDN (Power Delivery Network) parameter sensitivity analysis, which aims to address these challenges. By automating parameter sampling and utilizing metamodeling techniques, we can accelerate the exploration of PG grid parameters (e.g., metal pitch and width), enabling a more comprehensive and efficient sensitivity analysis. This methodology eliminates the need for repetitive simulations after the metamodel generation, thus reducing the iteration cycles traditionally required for power grid optimization. Our results demonstrate that ML-driven exploration helps identify key dependencies, such as the effect of metal pitch on voltage drop (DVD), and allows for signal routing congestion reduction. This approach also holds potential for optimizing PG grids with respect to other parameters, including frequency, activity, and power switch pitch, making it a versatile tool for SoC design optimization.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall