Presentation
Validation journey of SOC High Speed Interfaces: From sim to real device
DescriptionValidating high-speed peripherals, such as PCIe, presents a significant challenge in SoC design. Traditional simulation methods are often inadequate for achieving sufficient test coverage due to the high data rates involved. Consequently, design teams are increasingly adopting emulation and FPGA platforms. These platforms facilitate comprehensive testing using real-world device connectivity at great speed making high end data traffic possible, providing a substantial advantage over conventional simulation approaches.
This paper examines diverse PCIe validation methodologies, demonstrating the advantages of employing emulation and FPGA platforms in conjunction with physical hardware. The following aspects are explored:
Simulation with PCIe VIP: Provides fundamental verification capabilities but is constrained by speed limitations.
Emulation with a PCIe transactor: Offers enhanced speed performance but lacks interaction with real-world hardware components.
Emulation with a real PCIe device: Facilitates near-silicon validation using a standard hardware device.
Emulation with a PCIe-WLAN device: Enables testing within a specific use-case integration scenario.
Hybrid emulation with a PCIe-WLAN device: Integrates the adaptability of emulation with the precision of actual hardware implementation.
By prioritizing real hardware integration, these sophisticated platforms substantially enhance verification coverage, facilitating earlier bug detection and increasing confidence in the final System on a Chip (SoC). A genuine shift left in the validation process is achieved by attaining near-silicon validation coverage 6-8 months earlier using a Pre-Silicon platform.
This paper examines diverse PCIe validation methodologies, demonstrating the advantages of employing emulation and FPGA platforms in conjunction with physical hardware. The following aspects are explored:
Simulation with PCIe VIP: Provides fundamental verification capabilities but is constrained by speed limitations.
Emulation with a PCIe transactor: Offers enhanced speed performance but lacks interaction with real-world hardware components.
Emulation with a real PCIe device: Facilitates near-silicon validation using a standard hardware device.
Emulation with a PCIe-WLAN device: Enables testing within a specific use-case integration scenario.
Hybrid emulation with a PCIe-WLAN device: Integrates the adaptability of emulation with the precision of actual hardware implementation.
By prioritizing real hardware integration, these sophisticated platforms substantially enhance verification coverage, facilitating earlier bug detection and increasing confidence in the final System on a Chip (SoC). A genuine shift left in the validation process is achieved by attaining near-silicon validation coverage 6-8 months earlier using a Pre-Silicon platform.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
Front-End Design