Presentation
Design Quality Improvement Through Automation
DescriptionThe digital designs predominantly include Memory Mapped Registers (MMRs) to configure the design as per the application needs. Digital designs also contain multiple Finite State Machines (FSMs) and boundary ports. To verify basic feature-sets of a design, such as MMR reads and writes, boundary port drive based FSM state transitions and event generation logic, the designer has to rely on design verification (DV) feedback which may take significant amount of time more so with new designs. Hence in order to improve design quality and reduce IP development cycle time, the automation tool named Elementary Sanity Testing Aid for Designers (ESTAD) is developed and proposed in this presentation The proposed tool ESTAD enables designers to analyze their design quickly, both in waveform and source-code without needing DV feedback The automation creates a sanity testbench systemVerilog file with the inputs from an excel sheet and a component xml file This tool enables generation of waveform and also includes basic checkers in the testbench file.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall