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Building a Parallel Simulation Kernel for Faster & Better Virtual Platforms
DescriptionThe ASTC VLAB version 2 simulator/virtual platform tool was designed in the late 2000s. Based on the requirements of the time, it is based on a SystemC simulator kernel together with fast instruction-set simulators. As the complexity and processor core count of the hardware that is being modeled in VLAB increased over the years, performance was becoming an issue. To unlock performance for the future, it was necessary to move away from SystemC as the kernel.

A new simulator kernel, Hipersim, was created with the explicit goal of removing performance bottlenecks. It improves serial simulation performance and open up for parallel simulation (by removing the serial semantics imposed by SystemC). Along the way, the rest of the product was also redesigned to support performance – and clean out some old features. Still, the product had to remain compatible with existing ecosystem models and integrations.

This talk presents our experience implementing the new kernel and how it handles SystemC models and new models. We share some performance measurements and observations from the implementation process and porting of old models to the new kernel.

Submission category: SAS.04 Simulation and modeling environments