Presentation
Method of Static Timing Analysis for Dual Edge Triggered Pulsed Latches
DescriptionAs the demand for high-performance servers continues to grow, the use of dual edge clocking and high performance latches has become increasingly prevalent. However, the presence of these components poses significant challenges for static timing analysis (STA), which is a critical step in the design of digital circuits. In this paper, we present novel techniques for STA in the presence of dual edge clocking and high performance latches, enabling accurate analysis of both pulsed and transparent latches. Our approach leverages the unique properties of these components to improve the accuracy by reducing pessimism and efficiency of STA, allowing for more reliable and high-performance designs. We demonstrate the effectiveness of our techniques through a series of case studies and compare them to existing methods, showing significant improvements in accuracy and performance.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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