Presentation
Activity-Based Power Density Optimization
DescriptionThe need for high performance and increased feature addition in smaller areas is pushing the limits of physics in terms of process node optimization across the metrics of power/performance/area. While a higher number of transistors per unit area enables increased feature addition, it can create extreme power density hotspots due to higher switching activity. High performance processor core is one of the major IP which is affected by this trend of high-power density as the IP tries to achieve desired PPA goals of advanced process node. Since turbo frequency is a crucial factor to meet the performance benchmark, core IP voltage limit is closer to the process Vmax limit defined for reliability. These factors aggravate the issue of high-power density which leads to increased temperature ramp (Oc/ms) in the die and creation of localized hotspots. These kinds of localized hotspots may lead to permanent faults and reliability challenges. Advanced process nodes are required to meet power density targets to avoid thermal runaway scenarios. In this paper, we discuss power density mitigating techniques like module padding/instance padding and Activity-Based Power Density optimization on high switching designs.
This technique enables designers to reduce power density with minimal timing impact throughout the design cycle. The above techniques were tested in complex design with extremely high switching activity partition for next generation cores to reduce the power density by 40% in a thermal critical region.
This technique enables designers to reduce power density with minimal timing impact throughout the design cycle. The above techniques were tested in complex design with extremely high switching activity partition for next generation cores to reduce the power density by 40% in a thermal critical region.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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