Presentation
Solving Configuration Challenge with SVRAND Verification Flow
DescriptionCadence Memory Models use configuration files which describe the unique characterization attributes of every real memory part. The Memory Model appropriately performs timing checks and protocol responses appropriate to the characterization attributes described by each configuration. As the scale of configuration files for targeted Memory Model increases, a significant challenge arises for the EDA memory provider to accurately maintain and update these files for all varieties of real part configurations. Similarly, it becomes challenging for the users of the memory models to keep their repository snapshot of these configurations up to date while simultaneously selecting from and covering all these configurations with each simulation to ensure compatibility. Especially as part offerings even within one protocol have increased into the tens of thousands while the number of characterization attributes needed to describe a memory and the dependencies between them increases with each protocol generation. While verifying memory sub-systems, configuration process becomes lengthy, and it impacts resource on fixed interval. Existing configuration flow uses one part at a time in the simulation. New SVRAND flow provides flexibility to represent all valid parts in a single System Verilog class which resolves evenly across user's application scope of required configurations while simultaneously providing compatibility closure over that same scoped set of parts.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall