Presentation
Enhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros/IP and Standard Cell Libraries
DescriptionThis paper presents an advanced approach to cell-aware testing, focusing on defect-oriented methodologies to enhance IC reliability. Traditional fault models, such as stuck-at and transition faults, are insufficient for detecting latent defects in complex standard cells. The study introduces a methodology based on Layout Parasitic Extracted (LPE) netlists, leveraging SPICE simulations to model defects like bridging and open faults at a finer granularity.
A key improvement is the visualization of LPE netlists using Siemens CMG tools to ensure accurate extraction, reducing false defect reports and improving debugging. Additionally, critical regions in layouts are identified using timing analysis, enabling the creation of User Defined Fault Models (UDFM) that capture latent defects under various PVT and RC conditions.
The paper also highlights the importance of Cell Neighborhood Bridge (CNB) analysis, which detects inter-cell defects that conventional models overlook. By optimizing CMG settings and collaborating closely with foundries, the approach significantly enhances defect coverage.
This novel methodology has led to a twofold improvement in productivity by reducing IC design cycle times and improving test accuracy. The enhanced defect identification process contributes to lower Defective Parts Per Million (DPPM) rates, particularly in automotive applications.
A key improvement is the visualization of LPE netlists using Siemens CMG tools to ensure accurate extraction, reducing false defect reports and improving debugging. Additionally, critical regions in layouts are identified using timing analysis, enabling the creation of User Defined Fault Models (UDFM) that capture latent defects under various PVT and RC conditions.
The paper also highlights the importance of Cell Neighborhood Bridge (CNB) analysis, which detects inter-cell defects that conventional models overlook. By optimizing CMG settings and collaborating closely with foundries, the approach significantly enhances defect coverage.
This novel methodology has led to a twofold improvement in productivity by reducing IC design cycle times and improving test accuracy. The enhanced defect identification process contributes to lower Defective Parts Per Million (DPPM) rates, particularly in automotive applications.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall