Presentation
Single Corner Mixed Voltage Functional Noise Analysis
DescriptionFunctional or glitch noise analysis determines if coupling between switching "aggressor" wires and a steady-state "victim" wire could induce incorrect switching on the victim. This analysis is sensitive to the relative voltage of all victim and aggressor wires involved. Historically, most wires within the chip operate at a single common "worst-case" voltage level making library characterization, and simulation setup (i.e. voltage levels for victim and aggressor wires) relatively straight forward for a single corner sign-off functional noise run. However, modern chips with multiple co-located voltage regions along with Dynamic Voltage/Frequency Scaling (DVFS) can complicate the analysis by having wires in different variable voltage domains (i.e VDD1 and VDD2 each with independent min/max voltage ranges) next to each other. This creates multiple "worst-case" voltage conditions depending on victim-aggressor voltage domains and greatly challenges the ability to sign-off with a single corner analysis. We present a method for carefully adjusting aggressor wire voltages (relative to victim voltage level) to enable safe and complete functional noise analysis using a single corner noise library in a single analysis run.
Event Type
Engineering Poster
Networking
TimeWednesday, June 2512:15pm - 1:15pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall