Presentation
Formal meets Simulation: Accelerate Verification closure using Multiplatform technologies
DescriptionThis Paper leverages practical usage of UCIe/Chiplet systems as a live testimony - Formal verification and simulation/emulation verification of designs and proposes combining them for better results.
1. Formal Verification:
• Detects bugs early and allows reuse of tools across platforms.
• However, it struggles with large designs and deep-state exploration, making it less effective for complex scenarios.
2. Simulation/Emulation Verification:
• Handles large designs and deep-state simulations effectively.
• However, debugging issues can take days due to time-intensive failure analysis.
Hybrid Approach: Combining Both Methods
Running formal and simulation/emulation verification together offers the best of both worlds:
• Catch Early Bugs: Formal runs can quickly identify simple issues.
• Faster Debugging: Assertions from formal runs can be reused in simulations, stopping at failures to save time.
• Consistency: Using shared properties across both platforms ensures consistent checks and constraints.
• Accelerated Coverage: Merging formal coverage with simulation coverage helps achieve faster verification at the system-on-chip (SoC) level.
This hybrid approach shows results of both methods - Speed up and improve the overall verification process, ensuring more reliable results and hence improving TAT
1. Formal Verification:
• Detects bugs early and allows reuse of tools across platforms.
• However, it struggles with large designs and deep-state exploration, making it less effective for complex scenarios.
2. Simulation/Emulation Verification:
• Handles large designs and deep-state simulations effectively.
• However, debugging issues can take days due to time-intensive failure analysis.
Hybrid Approach: Combining Both Methods
Running formal and simulation/emulation verification together offers the best of both worlds:
• Catch Early Bugs: Formal runs can quickly identify simple issues.
• Faster Debugging: Assertions from formal runs can be reused in simulations, stopping at failures to save time.
• Consistency: Using shared properties across both platforms ensures consistent checks and constraints.
• Accelerated Coverage: Merging formal coverage with simulation coverage helps achieve faster verification at the system-on-chip (SoC) level.
This hybrid approach shows results of both methods - Speed up and improve the overall verification process, ensuring more reliable results and hence improving TAT
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall