Presentation
Detection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS)
DescriptionSystem-on-Chip (SoC) manufacturing at nanometer regimes is a very costly affair due to high mask cost. To avoid respins, most organizations employ an extensive digital and mixed-signal verification environment, running over thousands of simulations before tapeout. However, using digital and mixed-signal simulations may not uncover all the current related bugs in the SoC. For example, forward bias diode during different power ramp-up sequences, can prevent the device from powering up cannot be caught unless a Full-Chip-SPICE (FCS) simulation are run.
In this work, we will discuss an advanced verification method to verify full SoC at SPICE level. Verilog netlist dumped from PnR tool converted to CDLs is used for the simulation. Many techniques are used to make the scale of simulation manageable. PrimeSim XA from Synopsys is used as the simulator of choice that can simulate 100M+ transistors with reasonable runtime and good accuracy.
The following bugs were caught using this methodology 1) Excess supply current during a specific power-up sequence 2) Current beyond specs in low power mode 3) Extra leakage in standby mode due to wrong level of signal between two interacting analog IPs. 4) High crowbar current as isolation cell did not assert in standby mode, etc.
In this work, we will discuss an advanced verification method to verify full SoC at SPICE level. Verilog netlist dumped from PnR tool converted to CDLs is used for the simulation. Many techniques are used to make the scale of simulation manageable. PrimeSim XA from Synopsys is used as the simulator of choice that can simulate 100M+ transistors with reasonable runtime and good accuracy.
The following bugs were caught using this methodology 1) Excess supply current during a specific power-up sequence 2) Current beyond specs in low power mode 3) Extra leakage in standby mode due to wrong level of signal between two interacting analog IPs. 4) High crowbar current as isolation cell did not assert in standby mode, etc.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall