Presentation
3D-IC Heterogeneous System Implementation using Virtuoso Studio and Integrity System Planner
DescriptionAnalog and Photonic ICs are implemented in Virtuoso, where designers co-design stacks, perform EM analysis and use Packageless technology with Technology independent abstracts for IC footprints. These stacks are then integrated into larger systems in Integrity 3DIC, which may involve additional subsystems like other IC stacks, interposers, and packaging. This requires seamless transfer of the analog subsystem between Virtuoso and Integrity 3DIC, ensuring that changes made in one are seamlessly reflected in the other. This includes tasks like die positioning and optimal bump placement within the system context, etc. However, challenges arise due to differing die footprint formats, stack handling methods, and the complexity of advanced stacking (e.g., multiple ICs with cavities). Additionally, connectivity updates and bi-directional ECOs must be supported.
To address these challenges, we propose a mechanism that enables complete interoperability between Virtuoso and Integrity 3DIC. This flow ensures the seamless transfer of IC footprint, stacking, and connectivity information without data loss. Designers can implement, stack, edit, and analyze ICs in Virtuoso, developing subsystems that can be integrated into the full system in Integrity 3DIC. As photonic and complex stacking systems evolve, the proposed solution provides a robust framework for planning, implementation, bump management, and final sign-off.
To address these challenges, we propose a mechanism that enables complete interoperability between Virtuoso and Integrity 3DIC. This flow ensures the seamless transfer of IC footprint, stacking, and connectivity information without data loss. Designers can implement, stack, edit, and analyze ICs in Virtuoso, developing subsystems that can be integrated into the full system in Integrity 3DIC. As photonic and complex stacking systems evolve, the proposed solution provides a robust framework for planning, implementation, bump management, and final sign-off.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall