Presentation
A Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC Integration
DescriptionIn today's era of advanced application, SoC comprises of vast number of AMS IP due to advantages as 1.) Enhanced performance : High Speed Data Converters, Improved Signal Quality. 2). Complex & Diverse applications : IoT, Automotive and Industrial etc. 3). Innovation and Differentiation : New features, customization and flexibility. 4).Power efficiency (Low power, PMU), 5). Sensors and more…
Integration of such complex AMS IP in SoC Flow is challenging and cumbersome task. Here Library CAD views are pivotal in the complete SoC flow. Hardware Description Language (HDL) models are integral components of these CAD views IP libraries, which play important role in entire SoC (System on Chip) flow, starting from RTL to Emulation, Prototyping & Silicon debugging.
Given their importance, the verification of HDL models becomes a critical step in the overall CAD library development process. The diverse applications of HDL models in ASIC design flow necessitate robust and faster verification of all HDL views, including simulation models, test models, equivalence models, and timing models. Verifying these different views on separate platforms is a complex and time-consuming process. This work presents a verification suite for Analog Mixed Signal (AMS) IP's HDL models. It addresses the challenges associated with verifying all HDL views and introduces a robust and efficient approach. Through detailed test cases and comprehensive comparisons, the proposed methodology demonstrates significant improvements in the quality and efficiency of the verification process.
Integration of such complex AMS IP in SoC Flow is challenging and cumbersome task. Here Library CAD views are pivotal in the complete SoC flow. Hardware Description Language (HDL) models are integral components of these CAD views IP libraries, which play important role in entire SoC (System on Chip) flow, starting from RTL to Emulation, Prototyping & Silicon debugging.
Given their importance, the verification of HDL models becomes a critical step in the overall CAD library development process. The diverse applications of HDL models in ASIC design flow necessitate robust and faster verification of all HDL views, including simulation models, test models, equivalence models, and timing models. Verifying these different views on separate platforms is a complex and time-consuming process. This work presents a verification suite for Analog Mixed Signal (AMS) IP's HDL models. It addresses the challenges associated with verifying all HDL views and introduces a robust and efficient approach. Through detailed test cases and comprehensive comparisons, the proposed methodology demonstrates significant improvements in the quality and efficiency of the verification process.
Event Type
Engineering Poster
TimeTuesday, June 245:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall