Presentation
Machine Learning Based Layout Optimization of Electromagnetic Structures for High-Speed IO Design
DescriptionThe evolution of new technologies and applications are driving increasing chip complexity with reduced design cycles. For example, the increasing density of artificial intelligence (AI) and central processing unit (CPU) die are fueling an increase in the number of high-speed inputs and outputs (IOs). These IOs require electrostatic discharge (ESD) protection circuits where the ESD capacitance will limit signal speed if not properly compensated. The present design flow to compensate for the ESD capacitance is a very manual, time-consuming, and error-prone process.
Our new methodology proposes to automate this workflow with an adaptive metamodel of optimal prognosis (AMOP) optimizer that relies on a high-capacity electromagnetic modeling engine coupled with a circuit simulator to automatically size and place spiral devices to compensate for the ESD capacitance to find the optimal circuit performance. This reduces design cycle time (from weeks to hours) and manual effort and increases confidence that an optimal solution has been found. This flow also allows the structure to be revisited at all design milestones to validate early assumptions and ensure the optimal layout has been identified before tapeout. We use a 9.6 Gbps high-bandwidth memory read/write channel requiring the use of T-coils to demonstrate our thesis.
Our new methodology proposes to automate this workflow with an adaptive metamodel of optimal prognosis (AMOP) optimizer that relies on a high-capacity electromagnetic modeling engine coupled with a circuit simulator to automatically size and place spiral devices to compensate for the ESD capacitance to find the optimal circuit performance. This reduces design cycle time (from weeks to hours) and manual effort and increases confidence that an optimal solution has been found. This flow also allows the structure to be revisited at all design milestones to validate early assumptions and ensure the optimal layout has been identified before tapeout. We use a 9.6 Gbps high-bandwidth memory read/write channel requiring the use of T-coils to demonstrate our thesis.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall