Presentation
Real-time Process Margin-based Layout Optimization
DescriptionCreation of new special constructs, exploratory layouts, and design optimization is highly time and resource consuming. There is no layout design method which makes all relevant design information readily available. A layout design method which utilizes design information, design rule values, with the option to consider Si validated margin and AI predicted margin information and PEX/parasitics information. Design information will be available to the user in a layout overlay, updating in real-time with design/shape modifications, allowing for design optimization and creation of new special constructs. Margin information is obtained through Si validation experiments, as well as default (non-experimental) values determined by process assumption and DR calculations. PEX information is obtained from existing PEX tables and interpolated values. Exploratory design and margin prediction may reveal blind spots in design rule interactions, leading to PDK improvement. Also discussed is the methodology to predict design rule margin compaction opportunities, using machine learning applied to the Silicon validation data dataset.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall