Presentation
Method of Constraint Transformation in Static Timing Analysis for Dual Edge Timing
DescriptionWhen moving to new chip designs or new clocking schemas constraint creation is tedious, time consuming, and prone to human error. Typically, designers will use previous design constraints and manually modify when timing results do not provide correct output. This can be an iterative process.
A smart tool is needed for the designer that supports the complexity and error prone challenges of creating translated constraints. We propose a novel tool that automatically creates timing constraints based upon clock schemas and design topology. We show how our novel tool uses techniques for constraint transformation in the presence of dual edge clocking and improves the accuracy and efficiency of STA. We demonstrate the effectiveness of our techniques through implementation of constraint transformation from single edge clocking to dual edge clocking.
Jack DiLullo: EDA, IBM USA; Eric Foreman: EDA, IBM USA; Manish Verma: EDA, IBM India
A smart tool is needed for the designer that supports the complexity and error prone challenges of creating translated constraints. We propose a novel tool that automatically creates timing constraints based upon clock schemas and design topology. We show how our novel tool uses techniques for constraint transformation in the presence of dual edge clocking and improves the accuracy and efficiency of STA. We demonstrate the effectiveness of our techniques through implementation of constraint transformation from single edge clocking to dual edge clocking.
Jack DiLullo: EDA, IBM USA; Eric Foreman: EDA, IBM USA; Manish Verma: EDA, IBM India
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall