Presentation
High-Capacity, High-Performance Chip-Level ESD Analysis for Reliable Semiconductor Designs
DescriptionAnsys PathFinder-SC is the next-generation SoC and Analog Mixed Signal Design ESD reliability analysis platform designed to enable sub-16nm design success. In this slide, PathFinder-SC flow enables in verifying and signing-off full CHIP ESD checks for highly integrated multi-power/gnd domain SoCs. This flow demonstrates a high-capacity solution for verifying the protective circuitry found on production chip that protects from electrostatic discharge (ESD) by providing effective P2P resistance of ESD ZAP path and its current density analysis involving P/G nets as well as Signal nets that are challenging for performance of large SoC design. This technology has become increasingly pivotal as silicon technology continues to shrink to 3nm and below, where these tiny transistors
need to be protected by critical ESD circuitry that is checked, verified, and signed off with PathFinder-SC. PathFinder-SC is built on Ansys SeaScape, the world's first custom-designed big data platform for electronic system design and simulation. SeaScape provides per-core scalability, flexible design data access, instantaneous design bring-up, and many other revolutionary capabilities. SeaScape technology allows PathFinder-SC to deliver faster turnaround for ultra-large SoCs, which makes it ideal for today's large, high-speed semiconductor designs in Cloud Computing, Artificial intelligence, Imaging, Networking, and 5G and 6G telecommunications.
need to be protected by critical ESD circuitry that is checked, verified, and signed off with PathFinder-SC. PathFinder-SC is built on Ansys SeaScape, the world's first custom-designed big data platform for electronic system design and simulation. SeaScape provides per-core scalability, flexible design data access, instantaneous design bring-up, and many other revolutionary capabilities. SeaScape technology allows PathFinder-SC to deliver faster turnaround for ultra-large SoCs, which makes it ideal for today's large, high-speed semiconductor designs in Cloud Computing, Artificial intelligence, Imaging, Networking, and 5G and 6G telecommunications.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall