Presentation
Integrating Self-Heat Analysis in Multiphysics Simulation for Advanced Semiconductor Chip Design
DescriptionAdvancements in semiconductor technology are pushing the boundaries of chip design, but they also bring challenges like power losses and thermal impacts. Addressing these thermal issues early in the design process is crucial. We propose a Multiphysics simulation flow that integrates self-heat analysis with power integrity simulations, fitting into conventional chip design sign-off methodologies. This flow requires thermal resistance inputs, which can be obtained from the foundry or simulated separately. Our detailed simulation setup includes all necessary inputs and flows. In our example, the ambient temperature is set to 110°C. Self-heating causes the power grid net temperature to rise by about 3°C and the signal net temperature by about 8°C, increasing electromigration (EM) limits. We provide heatmaps and tables showing these temperature increases and their impact on EM limits. The entire simulation completes within 24 hours and meets existing chip design requirements. Early self-heat analysis helps identify electromigration variations and hot-spots, mitigating thermal issues before chip tape-out. This methodology will be used for advanced technology nodes.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall