Presentation
Advanced Yield Prediction for SRAM Bitcells with Rare Defect Modeling Leveraging AI-Powered Methodology
DescriptionAchieving high yield in SRAM bitcells is a critical challenge in semiconductor manufacturing, where process variations and random defects can significantly impact performance and reliability. This paper presents a novel methodology for improving SRAM yield prediction by integrating rare, random defects into traditional simulation models. The approach specifically addresses the impact of defects in NFET devices on SRAM performance, which were previously unquantified. Using an AI-powered methodology incorporates exponentially distributed defect variables and adjusts for variations in threshold voltage (Vt), enabling more accurate predictions of SRAM yield and fail-counts. The proposed method reduced the error margin in Vmin prediction to less than 5% and improved alignment between simulated and observed fail-counts. With minimal additional computational overhead, this AI-powered approach enhances the accuracy and efficiency of yield prediction for SRAM bitcells, offering a powerful tool for managing yield loss in advanced process nodes.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall