Presentation
Methodology to Generate Synthesis Signoff Quality Optimized Registers at RTL and Application of Generated Optimized Registers into RTL and Implementation Design Flows to Improve Productivity
DescriptionProblem Statement:
During synthesis, hundreds of thousands of registers are reported as optimized away, but there is no way to know the exact reason for optimization except the type of optimization like Constant optimization (C0r/C1r), Unloaded (ULR), Merged etc. There could be multiple reasons like optimizations due to direct RTL constants, toggling logic, optimized register might again be optimizing 100s of registers in its path indirectly, unloaded registers whose outputs are blocked or unused and registers having constant input sources or outputs are blocked or hanging. It can take several weeks of back and forth between RTL engineers and Synthesis engineers to validate and identify the root causes of the issue, fix, constrain or waive these before proceeding to Implementation. This affects productivity and efficiency, possibly affecting the design cycles.
Generation and Debug:
The proposed solution is to shift-left this process. VC SpyGlass IDC (Implementation Design Checks) is designed to use light weight synthesis engine of Fusion Compiler to determine which registers can possibly get optimized along with the RCA debug info, to give the RTL designers to quickly validate both unintended and intended optimized registers and fix RTL using Lint Advisor fix flow , generate constraints to preserve the design elements from constant propagation and generate waive database for the Intended optimized registers to migrate and use for signoff analysis.
Applications:
1. Improve Power Correlation: The generated signed off optimized registers database by VC SpyGlass IDC tool can feed to RTL Power Analysis tools to improve Power correlation between RTL and Gate level
2. Improve Coverage metrics: Same database can be used with Dynamic verification tools to improve coverage metrics
3. Improve Signoff effort: The generated Waiver Data Format (WDF) database with Fusion Compiler Flow to optimize the duplicate effort of validating issues which have already been validated and signed off at RTL level.
4. Help to better PPA: The generated constraints database can be used with Fusion Compiler to get accurate PPA results.
During synthesis, hundreds of thousands of registers are reported as optimized away, but there is no way to know the exact reason for optimization except the type of optimization like Constant optimization (C0r/C1r), Unloaded (ULR), Merged etc. There could be multiple reasons like optimizations due to direct RTL constants, toggling logic, optimized register might again be optimizing 100s of registers in its path indirectly, unloaded registers whose outputs are blocked or unused and registers having constant input sources or outputs are blocked or hanging. It can take several weeks of back and forth between RTL engineers and Synthesis engineers to validate and identify the root causes of the issue, fix, constrain or waive these before proceeding to Implementation. This affects productivity and efficiency, possibly affecting the design cycles.
Generation and Debug:
The proposed solution is to shift-left this process. VC SpyGlass IDC (Implementation Design Checks) is designed to use light weight synthesis engine of Fusion Compiler to determine which registers can possibly get optimized along with the RCA debug info, to give the RTL designers to quickly validate both unintended and intended optimized registers and fix RTL using Lint Advisor fix flow , generate constraints to preserve the design elements from constant propagation and generate waive database for the Intended optimized registers to migrate and use for signoff analysis.
Applications:
1. Improve Power Correlation: The generated signed off optimized registers database by VC SpyGlass IDC tool can feed to RTL Power Analysis tools to improve Power correlation between RTL and Gate level
2. Improve Coverage metrics: Same database can be used with Dynamic verification tools to improve coverage metrics
3. Improve Signoff effort: The generated Waiver Data Format (WDF) database with Fusion Compiler Flow to optimize the duplicate effort of validating issues which have already been validated and signed off at RTL level.
4. Help to better PPA: The generated constraints database can be used with Fusion Compiler to get accurate PPA results.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall