Presentation
Reusable and Efficient Scoreboard Implementation for bug hunting and testbench productivity
DescriptionScoreboard is an integral Universal Verification Component (UVC) in a Testbench infrastructure which helps to decide whether the DUT is functioning correctly or not. There are primarily two functionalities within a scoreboard: prediction and evaluation through which it determines the DUT correctness. But with the rising chip complexity, shrinking time to market demands, and the need to verify more features, coding an efficient and reusable scoreboard is the urgent need of the hour since it is one of the difficult blocks within a testbench.
The motivation behind writing this paper is to present an efficient, reusable, and time-critical scoreboard that can be used across IP and subsystem levels without minimal code modification. The proposed scoreboard architecture uses a hybrid approach which first separates the predictor or the reference model from the scoreboard to make it reusable. After that, it uses the mix of uvm analysis imp declaration macros and a combination of queues and tlm analysis fifo to handle the Inorder, Out of order and Inorder Producer comparison to make it efficient.
Finally, the proposed architecture also takes the help of Complexity theory and breaks a problem into P, NP, and NP-Hard problem which includes Greedy and Brute force algorithm to quickly verify stimulus which makes it time critical and helps to meet the time to market needs.
The motivation behind writing this paper is to present an efficient, reusable, and time-critical scoreboard that can be used across IP and subsystem levels without minimal code modification. The proposed scoreboard architecture uses a hybrid approach which first separates the predictor or the reference model from the scoreboard to make it reusable. After that, it uses the mix of uvm analysis imp declaration macros and a combination of queues and tlm analysis fifo to handle the Inorder, Out of order and Inorder Producer comparison to make it efficient.
Finally, the proposed architecture also takes the help of Complexity theory and breaks a problem into P, NP, and NP-Hard problem which includes Greedy and Brute force algorithm to quickly verify stimulus which makes it time critical and helps to meet the time to market needs.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall