Presentation
Interconnection Testkeys Enable BEOL-Process Monitoring and RC Accuracy Improvement
DescriptionAs ICs continue to evolve towards advanced nodes, the metal layer manufacturing processes and the parasitic resistance and capacitance between interconnects increasingly impact the overall performance of the design. Typically, to ensure the universality and yield of metal layer manufacturing processes, fabs provide conservative design rules and rough model files. This leads to a large real margin and a low accuracy of parasitic parameter in actual circuits.
To address these issues, we conduct research on interconnect testkey in the back-end metal layers. By designing testkeys with specific dimensions and structures, we evaluate potential risks in the manufacturing process, such as metal line Bridges, Opens, etc. Additionally, we further analyze the consistency between testkey simulation and test results to determine the deviation levels of parasitic parameter under different structures. This helps differentiate the advantages and disadvantages of different design solutions, providing references for subsequent similar designs. This research effectively identifies risks between interconnects and fully monitors the process platform's state. It also allows for the selection of different interconnect design solutions and improves the accuracy of parasitic parameter extraction. Through this work, we can thoroughly explore the real margin and provide an optimal design, thereby enhancing the competitiveness of the product.
To address these issues, we conduct research on interconnect testkey in the back-end metal layers. By designing testkeys with specific dimensions and structures, we evaluate potential risks in the manufacturing process, such as metal line Bridges, Opens, etc. Additionally, we further analyze the consistency between testkey simulation and test results to determine the deviation levels of parasitic parameter under different structures. This helps differentiate the advantages and disadvantages of different design solutions, providing references for subsequent similar designs. This research effectively identifies risks between interconnects and fully monitors the process platform's state. It also allows for the selection of different interconnect design solutions and improves the accuracy of parasitic parameter extraction. Through this work, we can thoroughly explore the real margin and provide an optimal design, thereby enhancing the competitiveness of the product.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall
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