Presentation
Streamlined RTL Clock Management: A Python Framework for Clock Tracing, Clock Spec Verification and STA Constraint Generation
DescriptionThis paper addresses the challenges of managing clock specifications, RTL implementation, and timing constraints in the development of subchip/block-based SoC designs.
Traditionally, discrepancies between clock specifications, RTL, and timing constraints are identified manually post-synthesis or even late in the development phase, leading to inefficient feedback loops.
In a parallel development environment, subchip physical design (PD) owners manually generate clock architecture diagrams and timing constraints based on the top-level clock spec and RTL.
This paper presents a Python-based framework that automates the generation of subchip-level clock architecture diagrams and clock timing constraints through RTL tracing.
By enabling early detection of discrepancies, this solution ensures better quality control across specifications, RTL, and timing constraints, and accelerates subchip PD execution by providing clock-related constraints even before subchip execution begins.
Traditionally, discrepancies between clock specifications, RTL, and timing constraints are identified manually post-synthesis or even late in the development phase, leading to inefficient feedback loops.
In a parallel development environment, subchip physical design (PD) owners manually generate clock architecture diagrams and timing constraints based on the top-level clock spec and RTL.
This paper presents a Python-based framework that automates the generation of subchip-level clock architecture diagrams and clock timing constraints through RTL tracing.
By enabling early detection of discrepancies, this solution ensures better quality control across specifications, RTL, and timing constraints, and accelerates subchip PD execution by providing clock-related constraints even before subchip execution begins.
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall