Presentation
Enhancing Timing Closure in High-Frequency Designs through Precise Latency Control and Timing-Aware Sink Assignment
DescriptionDesigns with latches have their own challenges while doing timing and power optimization in place and route flow. Challenges become more severe when latches are used at interfaces of different blocks.
Latch transparency makes PNR tools to balance internal and external timing points optimization difficult
Many timing paths goes through different partitions having latches at the interface and these interface latches need to meet specific clock latency targets to meet the timing but EDA PNR tools face difficulties in performing clock tuning (CCD) on these latches. This makes controlling the clock on interface sequential elements essential to meet the timing requirement during Clock tree synthesis (CTS).
To meet above requirements, we propose two approaches in clock tree
1) Precise Latency Landing on interface sequential using skew group and enhanced tool algorithm
2) Timing and Placement Aware Sink Assignments in Multi Source CTS
With These proposed approaches we were able to meet the required insertion delay target on 1% sequential of design, 28% hold TNS improvement and 24% improvement in setup TNS
Latch transparency makes PNR tools to balance internal and external timing points optimization difficult
Many timing paths goes through different partitions having latches at the interface and these interface latches need to meet specific clock latency targets to meet the timing but EDA PNR tools face difficulties in performing clock tuning (CCD) on these latches. This makes controlling the clock on interface sequential elements essential to meet the timing requirement during Clock tree synthesis (CTS).
To meet above requirements, we propose two approaches in clock tree
1) Precise Latency Landing on interface sequential using skew group and enhanced tool algorithm
2) Timing and Placement Aware Sink Assignments in Multi Source CTS
With These proposed approaches we were able to meet the required insertion delay target on 1% sequential of design, 28% hold TNS improvement and 24% improvement in setup TNS
Event Type
Engineering Poster
Networking
TimeMonday, June 235:00pm - 6:00pm PDT
LocationEngineering Posters, Level 2 Exhibit Hall